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AMI Semiconductor, Inc.
ULP Memory Solutions 670 North McCarthy Blvd. Suite 220 Milpitas, CA 95035 PH: 408-935-7777, FAX: 408-935-7770
N08M1618L1A
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8Mb Ultra-Low Power Asynchronous Medical CMOS SRAM
512K x 16 bit Overview
The N08M1618L1A is an integrated memory device intended for non life-support medical applications. This device is a 8 megabit memory organized as 524,288 words by 16 bits. The device is designed and fabricated using AMI Semiconductor's advanced CMOS technology with reliability inhancements for medical users. The device operates with two chip enable (CE1 and CE2) controls and output enable (OE) to allow for easy memory expansion. Byte controls (UB and LB) allow the upper and lower bytes to be accessed independently and can also be used to deselect the device. This device is optimal for various applications where low-power is critical such as battery backup and hand-held devices. The device can operate over a very wide temperature range of -40oC to +85oC and is available in a JEDEC standard BGA package.
Features
* Dual voltage for Optimum Performance: Vccq - 2.3 to 3.6 Volts Vcc - 1.4 to 2.2 Volts * Very low standby current 0.5A at 1.8V and 37 deg C * Very low operating current 1.0mA at 1.8V and 1s (Typical) * Very low Page Mode operating current 0.5mA at 1.8V and 1s (Typical) * Simple memory control Dual Chip Enables (CE1 and CE2) Byte control for independent byte operation Output Enable (OE) for memory expansion * Low voltage data retention Vcc = 1.2V * Special Processing to reduce Soft Error Rate (SER) * Automatic power down to standby mode
Product Family
Part Number Package Type Operating Temperature Power Supply Speed Standby Operating Current (ISB), Current (Icc), Max Max
N08M1618L1AB
48 - BGA 2.3V-3.6V(VCCQ) 85ns @ 1.7V -40oC to +85oC 1.4V-2.2V(V ) 150ns @ 1.4V CC 20 A 2.5 mA @ 1MHz
N08M1618L1AW
Wafer
Pin Configuration
1 A B C D E F G H
LB I/O8 I/O9 VSS
Pin Descriptions
3
A0 A3 A5 A17 NC A14 A12 A9
2
OE UB I/O10 I/O11
4
A1 A4 A6 A7 A16 A15 A13 A10
5
A2 CE1 I/O1 I/O3 I/O4 I/O5 WE A11
6
CE2 I/O0 I/O2 VCC VSS I/O6 I/O7 NC
Pin Name A0-A18 WE CE1, CE2 OE LB UB I/O0-I/O15 VCC VSS VCCQ NC
Pin Function Address Inputs Write Enable Input Chip Enable Input Output Enable Input Lower Byte Enable Input Upper Byte Enable Input Data Inputs/Outputs Power Ground Power I/O pins only Not Connected
VCCQ I/O12 I/O14 I/O13 I/O15 A18 NC A8
48 Pin BGA (top) 8 x 10 mm
Stock No. 23211-03 9/21/06 ADVANCE INFORMATION The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.
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AMI Semiconductor, Inc. Functional Block Diagram Address Inputs A0 - A3 Word Address Decode Logic
N08M1618L1A
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Address Inputs A4 - A18
Page Address Decode Logic
32K Page x 16 word x 16 bit RAM Array
Input/ Output Mux and Buffers
Word Mux
I/O0 - I/O7
I/O8 - I/O15 CE1 CE2 WE OE UB LB
Control Logic
Functional Description
CE1 H X X L L L CE2 X L X H H H WE X X X L H H OE X X X X3 L H UB X X H L1 L1 L1 LB X X H L1 L1 L1 I/O0 - I/O151 High Z High Z High Z Data In Data Out High Z MODE Standby2 Standby2 Standby2 Write3 Read Active POWER Standby Standby Standby Active -> Standby4 Active -> Standby4 Standby4
1. When UB and LB are in select mode (low), I/O0 - I/O15 are affected as shown. When LB only is in the select mode only I/O0 - I/O7 are affected as shown. When UB is in the select mode only I/O8 - I/O15 are affected as shown. 2. When the device is in standby mode, control inputs (WE, OE, UB, and LB), address inputs and data input/outputs are internally isolated from any external influence and disabled from exerting any influence externally. 3. When WE is invoked, the OE input is internally disabled and has no effect on the circuit. 4. The device will consume active power in this mode whenever addresses are changed. Data inputs are internally isolated from any expernal influence.
Capacitance1
Item Input Capacitance I/O Capacitance Symbol CIN CI/O Test Condition VIN = 0V, f = 1 MHz, TA = 25oC VIN = 0V, f = 1 MHz, TA = 25oC Min Max 8 8 Unit pF pF
1. These parameters are verified in device characterization and are not 100% tested
Stock No. 23211-03 9/21/06 ADVANCE INFORMATION The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.
2
AMI Semiconductor, Inc. Absolute Maximum Ratings1
Item Voltage on any pin relative to VSS Voltage on VCC Supply Relative to VSS Power Dissipation Storage Temperature Operating Temperature Soldering Temperature and Time Symbol VIN,OUT VCC PD TSTG TA TSOLDER
N08M1618L1A
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Rating -0.3 to VCC+0.3 -0.3 to 4.5 500 -40 to 125 -40 to +85 240oC, 10sec(Lead only)
Unit V V mW
o
C
oC oC
1. Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Operating Characteristics (Over Specified Temperature Range)
Item Core Supply Voltage I/O Supply Voltage Data Retention Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Leakage Current Output Leakage Current Read/Write Operating Supply Current @ 1 s Cycle Time2 Read/Write Operating Supply Current @ 85 ns Cycle Time2 Page Mode Operating Supply Current @ 85 ns Cycle Time2 (Refer to Power Savings with Page Mode Operation diagram) Read/Write Quiescent Operating Supply Current3 Symbol VCC VCCQ VDR VIH VIL VOH VOL ILI ILO ICC1 ICC2 IOH = 0.2mA IOL = -0.2mA VIN = 0 to VCC OE = VIH or Chip Disabled VCC=2.2 V, VIN=VIH or VIL Chip Enabled, IOUT = 0 VCC=2.2 V, VIN=VIH or VIL Chip Enabled, IOUT = 0 VCC=2.2 V, VIN=VIH or VIL Chip Enabled, IOUT = 0 VCC=2.2 V, VIN=VIH or VIL Chip Enabled, IOUT = 0, f=0 VIN = VCC or 0V Chip Disabled tA= 85oC, VCC = 2.2 V VCC = 1.2V, VIN = VCC or 0 Chip Disabled, tA= 85oC 1.5 10.0 VCCQ > or = VCC Chip Disabled3 Test Conditions Min. 1.4 2.3 1.2 VCCQ-0.6 -0.3 VCCQ-0.2 0.2 0.1 0.1 2.5 13.0 VCCQ+0.3 0.6 Typ1 1.8 Max 2.2 3.6 Unit V V V V V V V A A mA mA
ICC3
3.5
mA
ICC4
1
A
Standby
Current3
ISB1
0.5
20.0
A
Data Retention Current3
IDR
0.1
1.0
A
1. Typical values are measured at Vcc=Vcc Typ., TA=25C and not 100% tested. 2. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current required to drive output capacitance expected in the actual system. 3. This device assumes a standby mode if the chip is disabled (CE1 high or CE2 low). In order to achieve low standby current all inputs must be within 0.2 volts of either VCC or VSS.
Stock No. 23211-03 9/21/06 ADVANCE INFORMATION The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.
3
AMI Semiconductor, Inc. Power Savings with Page Mode Operation (WE = VIH)
N08M1618L1A
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Page Address (A4 - A18)
Open page ...
Word Address (A0 - A3)
Word 1
Word 2
Word 16
CE1 CE2
OE
Note: Page mode operation is a method of addressing the SRAM to save operating current. The internal organization of the SRAM is optimized to allow this unique operating mode to be used as a valuable power saving feature. The only thing that needs to be done is to address the SRAM in a manner that the internal page is left open and 8-bit words of data are read from the open page. By treating addresses A0-A3 as the least significant bits and addressing the 16 words within the open page, power is reduced to the page mode value which is considerably lower than standard operating currents for low power SRAMs.
Stock No. 23211-03 9/21/06 ADVANCE INFORMATION The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.
4
AMI Semiconductor, Inc. Timing Test Conditions
Item Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Levels Output Load Operating Temperature
N08M1618L1A
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0.1VCC to 0.9 VCC 5ns 0.5 VCC CL = 30pF -40 to +85 oC
Timing VCCQ > or = VCC
Item Read Cycle Time Address Access Time Address Access Time (Page Mode) Chip Enable to Valid Output Output Enable to Valid Output Byte Select to Valid Output Chip Enable to Low-Z output Output Enable to Low-Z Output Byte Select to Low-Z Output Chip Disable to High-Z Output Output Disable to High-Z Output Byte Select Disable to High-Z Output Output Hold from Address Change Write Cycle Time Chip Enable to End of Write Address Valid to End of Write Byte Select to End of Write Write Pulse Width Address Setup Time Write Recovery Time Write to High-Z Output Data to Write Time Overlap Data Hold from Write Time End Write to Low-Z Output Symbol tRC tAA tAAP tCO tOE tLB, tUB tLZ tOLZ tLBZ, tUBZ tHZ tOHZ tLBHZ, tUBHZ tOH tWC tCW tAW tLBW, tUBW tWP tAS tWR tWHZ tDW tDH tOW 50 0 10 20 20 20 0 0 0 20 150 75 75 75 50 0 0 30 40 0 5 30 30 30 VCC = 1.4 - 2.2 V Min. 150 150 30 150 50 150 10 5 10 0 0 0 10 85 50 50 50 40 0 0 15 15 15 15 Max. VCC = 1.7 - 2.2 V Min. 85 85 30 85 40 85 Max. Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Stock No. 23211-03 9/21/06 ADVANCE INFORMATION The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.
5
AMI Semiconductor, Inc. Timing of Read Cycle (CE1 = OE = VIL, WE = CE2 = VIH)
tRC Address tAA tOH
N08M1618L1A
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Data Out
Previous Data Valid
Data Valid
Timing Waveform of Read Cycle (WE=VIH)
tRC Address
tAA
tHZ(1,2)
CE1 tCO CE2 tLZ(2) tOE OE tOLZ tLB, tUB LB, UB tLBLZ, tUBLZ Data Out High-Z tLBHZ, tUBHZ Data Valid tOHZ(1)
Stock No. 23211-03 9/21/06 ADVANCE INFORMATION The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.
6
AMI Semiconductor, Inc. Timing Waveform of Page Mode Read Cycle (WE = VIH)
tRC Page Address (A4 - A18) tAA Word Address (A0 - A3) tAAP
N08M1618L1A
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tHZ CE1 tCO CE2 tOHZ
tOE OE tOLZ LB, UB tLBLZ, tUBLZ Data Out High-Z tLB, tUB
tLBHZ, tUBHZ
Stock No. 23211-03 9/21/06 ADVANCE INFORMATION The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.
7
AMI Semiconductor, Inc. Timing Waveform of Write Cycle (WE control)
tWC Address tAW CE1 tCW CE2 tLBW, tUBW LB, UB tAS WE tDW High-Z Data In tWHZ Data Out tWP
N08M1618L1A
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tWR
tDH
Data Valid tOW High-Z
Stock No. 23211-03 9/21/06 ADVANCE INFORMATION The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.
8
AMI Semiconductor, Inc. Timing Waveform of Write Cycle (CE1 Control)
tWC Address tAW CE1 (for CE2 Control, use inverted signal) LB, UB tWP WE tDW Data In tLZ Data Out tWHZ tCW tAS tLBW, tUBW
N08M1618L1A
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tWR
tDH
Data Valid
High-Z
Stock No. 23211-03 9/21/06 ADVANCE INFORMATION The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.
9
AMI Semiconductor, Inc. Ball Grid Array Package
A1 BALL PAD CORNER (3) D 0.200.05 1.100.10
N08M1618L1A
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1. 0.300.05 DIA. E 2. SEATING PLANE - Z 0.15 Z 0.05 TOP VIEW SIDE VIEW 1. DIMENSION IS MEASURED AT THE A1 BALL PAD MAXIMUM SOLDER BALL DIAMETER. CORNER PARALLEL TO PRIMARY Z. 2. PRIMARY DATUM Z AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 3. A1 BALL PAD CORNER I.D. TO BE MARKED BY INK. K TYP J TYP e Z
SD
e SE
BOTTOM VIEW
Dimensions (mm)
e = 0.75 D 80.10 E SD 100.10 0.375 SE 0.375 J 2.125 K 2.375 BALL MATRIX TYPE FULL
Stock No. 23211-03 9/21/06 ADVANCE INFORMATION The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.
10
AMI Semiconductor, Inc. Ordering Information
N08M1618L1A
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N08M1618L1AX-XX X
Temperature
I = Industrial, -40C to 85C
Performance
85 = 85ns @ 1.7V
Package Type
B = 48-ball BGA D = Known Good Die
Revision History
Revision # 01 Date 11/01/02 Initial Release General Update: Updated ICC4 typical and ISB1 typical value Updated Block Diagram, Functional Description Table. Added tAAP, tLB, tUB, tLBZ, tUBZ, tLBHZ, tUBHZ, tLBW, tUBW timing parameters. Added Page Mode Read Timing Waveform Updated BGA 8X10 Package Drawing Updated VccQ range on DC Parameters Table Converted to AMI Semiconductor Change Description
02
3/03/05
03
9/21/2006
(c) 2006 AMI Semiconductor, Inc. All rights reserved. AMI Semiconductor, Inc. ("AMIS") reserves the right to change or modify the information contained in this data sheet and the products described therein, without prior notice. AMIS does not convey any license under its patent rights nor the rights of others. Charts, drawings and schedules contained in this data sheet are provided for illustration purposes only and they vary depending upon specific applications. AMIS makes no warranty or guarantee regarding suitability of these products for any particular purpose, nor does AMIS assume any liability arising out of the application or use of any product or circuit described herein. AMIS does not authorize use of its products as critical components in any application in which the failure of the AMIS product may be expected to result in significant injury or death, including life support systems and critical medical instruments.
Stock No. 23211-03 9/21/06 ADVANCE INFORMATION The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.
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